1. Technical Field
Various embodiments generally relate to a semiconductor device, and more particularly, to a semiconductor device including dummy mats.
2. Related Art
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) includes a large number of memory cells. The number of memory cells gradually increases as processing technologies have developed and thus the degree of integration has been augmented. If even any one among such memory cells fails, a semiconductor memory device including the failed memory cell is discarded because the semiconductor device may not be able to perform all required operations.
Recently, as processing technologies for manufacturing semiconductor memory devices has developed, failures occur probabilistically in only a small number of memory cells. When considering a manufacturing yield, it is inefficient to discard an entire semiconductor memory device as a bad product due to such a small number of fails.
Thus, in order to cope with this problem, redundancy memory cells are included in a semiconductor memory device in addition to normal memory cells.
A redundancy memory cell is a circuit which repairs a failed memory cell (hereinafter, referred to as a “repair target memory cell”) when a failure occurs in a normal memory cell.
More specifically, for example, in read and write operations, when a target memory cell is repaired, not the repaired target memory cell but a normal memory cell is accessed internally. In this case, the accessed memory cell is a redundancy memory cell.
Accordingly, when an address corresponding to a repair target memory cell is inputted a semiconductor memory device, the semiconductor memory device performs an operation for accessing a redundancy memory cell (hereinafter, referred to as a “repair operation”) and not the repair target memory cell. Through such a repair operation, the semiconductor memory device is ensured normal operation.
A redundancy circuit for a repair operation is generally included in each of a plurality of banks which are included in a semiconductor memory device. Each bank includes a cell mat which is configured by a plurality of unit cells, a row control region which includes circuits for controlling row accesses, and a column control region which includes circuits for controlling column accesses.
The redundancy circuit includes a row redundancy circuit for repairing the row address of a failed unit cell, and a column redundancy circuit for repairing the column address of the failed unit cell. The row redundancy circuit and the column redundancy circuit are respectively included in the row control region and the column control region of each bank.